ELEN 6350 — VLSI Design

Tutorials

#	Topic	PDF
Tutorial01	Intro & Sample Project	↓
Tutorial02	HSPICE Simulation	↓
Tutorial03	Verilog Synthesis & Static Timing Analysis	↓
Tutorial04	Standard Cell Design	↓
Tutorial05	Block-level APR & SRAM Integration	↓
Tutorial06	Top-level APR	↓

RTL-to-GDSII verification status board for the course project. Tracks each module across simulation, synthesis, PNR, timing, and DRC/LVS stages.